Intel® Product Specification Comparison
03/29/2025 01:56:19 PM
 ,Intel Agilex® 5 FPGA E-Series 065B (B32A) ,Intel Agilex® 5 FPGA E-Series 065B (B23A) ,Intel Agilex® 5 FPGA E-Series 065A (B32A) ,Intel Agilex® 5 FPGA E-Series 065A (B23A) ,Intel Agilex® 5 FPGA E-Series 013B (B23A) ,Intel Agilex® 5 FPGA E-Series 013B (B32A) ,Intel Agilex® 5 FPGA E-Series 013A (B23A) ,Intel Agilex® 5 FPGA E-Series 013A (B32A) ,Intel Agilex® 5 FPGA E-Series 008B (B23A) ,Intel Agilex® 5 FPGA E-Series 013B (M16A) ,Intel Agilex® 5 FPGA E-Series 008B (M16A) ,Intel Agilex® 5 FPGA E-Series 008B (B32A) ,Intel Agilex® 5 FPGA E-Series 013B (B23B) ,Intel Agilex® 5 FPGA E-Series 008B (B23B) ,Intel Agilex® 5 FPGA E-Series 052B (B32A) ,Intel Agilex® 5 FPGA E-Series 043A (B32A) ,Intel Agilex® 5 FPGA E-Series 043B (B23A) ,Intel Agilex® 5 FPGA E-Series 052B (B23A) ,Intel Agilex® 5 FPGA E-Series 052A (B23A) ,Intel Agilex® 5 FPGA E-Series 052A (B32A) ,Intel Agilex® 5 FPGA E-Series 043B (B32A) ,Intel Agilex® 5 FPGA E-Series 043A (B23A) 
Essentials
Marketing Status,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched,Launched
Launch Date,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22,Q3'22
Lithography,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7,Intel 7

Resources
Logic Elements (LE),656080,656080,656080,656080,138060,138060,138060,138060,85196,138060,85196,85196,138060,85196,523920,434240,434240,523920,523920,523920,434240,434240
Adaptive Logic Modules (ALM),222400,222400,222400,222400,46800,46800,46800,46800,28880,46800,28880,28880,46800,28880,177600,147200,147200,177600,177600,177600,147200,147200
Adaptive Logic Module (ALM) Registers,889600,889600,889600,889600,187200,187200,187200,187200,115520,187200,115520,115520,187200,115520,710400,588800,588800,710400,710400,710400,588800,588800
Fabric and I/O Phase-Locked Loops (PLLs),21,21,21,21,12,12,12,12,12,12,12,12,12,12,21,19,19,21,21,21,19,19
Maximum Embedded Memory,38.25 Mb,38.25 Mb,38.25 Mb,38.25 Mb,8.42 Mb,8.42 Mb,8.42 Mb,8.42 Mb,5.56 Mb,8.42 Mb,5.56 Mb,5.56 Mb,8.42 Mb,5.56 Mb,30.31 Mb,24.61 Mb,24.61 Mb,30.31 Mb,30.31 Mb,30.31 Mb,24.61 Mb,24.61 Mb
Digital Signal Processing (DSP) Blocks,846,846,846,846,188,188,188,188,116,188,116,116,188,116,676,564,564,676,676,676,564,564
Digital Signal Processing (DSP) Format,Multiply |  Multiply and Accumulate |  Variable Precision |  Fixed Point (hard IP) |  Floating Point (hard IP),Multiply |  Multiply and Accumulate |  Variable Precision |  Fixed Point (hard IP) |  Floating Point (hard IP),Multiply |  Multiply and Accumulate |  Variable Precision |  Fixed Point (hard IP) |  Floating Point (hard IP),Multiply |  Multiply and Accumulate |  Variable Precision |  Fixed Point (hard IP) |  Floating Point (hard IP),Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision,Fixed Point (hard IP) |  Floating Point (hard IP) |  Multiply |  Multiply and Accumulate |  Variable Precision
Peak INT8 (TOPS),22.17,22.17,25.99,25.99,4.93,4.93,5.78,5.78,3.05,4.93,3.05,3.05,4.93,3.05,17.72,17.33,14.78,17.72,20.78,20.78,14.78,17.33
Hard Processor System (HPS),Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55,Dual core Arm* Cortex* -A76 |  Dual core Arm* Cortex* -A55
Hard Memory Controllers,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes
External Memory Interfaces (EMIF),DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  DDR5 |  LPDDR4 |  LPDDR5,DDR4 |  DDR5 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  DDR5 |  LPDDR4 |  LPDDR5,DDR4 |  DDR5 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  DDR5 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  DDR5 |  LPDDR4 |  LPDDR5,DDR4 |  DDR5 |  LPDDR4 |  LPDDR5,DDR4 |  LPDDR4 |  LPDDR5,DDR4 |  DDR5 |  LPDDR4 |  LPDDR5

I/O Specifications
Maximum User I/O Count†,504,216,504,216,216,392,216,392,216,232,232,392,352,352,504,504,216,216,216,504,504,216
I/O Standards Support,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling,1.2 V LVCMOS |  1.8 V LVCMOS |  SSTL |  POD |  HSTL |  HSUL |  Differential SSTL |  Differential POD |  Differential HSTL |  Differential HSUL |  True Differential Signaling
Maximum LVDS Pairs,192,192,192,192,96,96,96,96,48,96,48,48,96,48,192,192,192,192,192,192,192,192
Maximum Non-Return to Zero (NRZ) Transceivers†,24,12,24,12,4,4,4,4,4,4,4,4,,,24,16,12,12,12,24,16,12
Maximum Non-Return to Zero (NRZ) Data Rate†,28.1 Gbps,28.1 Gbps,28.1 Gbps,28.1 Gbps,17.16 Gbps,17.16 Gbps,28.1 Gbps,28.1 Gbps,17.16 Gbps,17.16 Gbps,17.16 Gbps,17.16 Gbps,,,17.16 Gbps,28.1 Gbps,17.16 Gbps,17.16 Gbps,28.1 Gbps,28.1 Gbps,17.16 Gbps,28.1 Gbps
Transceiver Protocol Hard IP,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4,PCIe Gen4

Advanced Technologies
Hyper-Registers,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes
FPGA Bitstream Security,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes,Yes

Package Specifications
Package Options,B32A,B23A,B32A,B23A,B23A,B32A,B23A,B32A,B23A,M16A,M16A,B32A,B23B,B23B,B32A,B32A,B23A,B23A,B23A,B32A,B32A,B23A

Supplemental Information
Additional Information,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation,Product Table (Family Comparison) Datasheet All FPGA Documentation
